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| PRELIMINARY DATA SHEET 256MB 32-bit Direct Rambus DRAM RIMM Module EBR25UC8ABKD (64M words x 16 bits x 2 channels) Description The 32-bit Direct Rambus RIMM module is a generalpurpose high-performance lines of memory modules suitable for use in a broad range of applications including computer memory, personal computers, workstations, and other applications where high bandwidth and latency are required. The EBR25UC8ABKD consists of 8 pieces of 288Mb Direct Rambus DRAM (Direct RDRAM) devices. These are extremely high-speed CMOS DRAMs organized as 16M words by 18 bits. The use of Rambus Signaling Level (RSL) technology permits the use of conventional system and board design technologies. The 32-bit RIMM modules support 1066MHz or 800MHz transfer rate per pin, resulting in total module bandwidth of 3.2GB/s. The 32-bit RIMM module provides two independent 16 bit memory channels to facilitate compact system design. The "Thru" Channel enters and exits the module to support a connection to or from a controller, memory slot, or termination. The "Term" Channel is terminated on the module and supports a connection from a controller or another memory slot. Features * 256MB Direct RDRAM storage and 256 banks total on module * 2 independent Direct RDRAM channels, 1 pass through and 1 terminated on 32-bit RIMM module * High speed 1066MHz / 800MHz Direct RDRAM devices * 232 edge connector pads with 1mm pad spacing Module PCB size: 133.35mm x 34.925mm x 1.27mm Gold plated edge connector pads contacts * Serial Presence Detect (SPD) support * Operates from a 2.5V supply * Low power and power down self refresh modes * Separate Row and Column buses for higher efficiency * RDRAMs uses Chip Scale Package (CSP) FBGA package EO The RDRAM architecture enables the highest sustained bandwidth for multiple, simultaneous, randomly addressed memory transactions. The separate control and data buses with independent row and column control yield over 95% bus efficiency. The RDRAM device multi-bank architecture supports up to four simultaneous transactions per device. Document No. E0309E11 (Ver. 1.1) Date Published March 2006 (K) Japan URL: http://www.elpida.com L This product became EOL in May, 2004. Elpida Memory, Inc. 2002-2006 Pr od uc t EBR25UC8ABKD Ordering Information Part number EBR25UC8ABKD-AEP EBR25UC8ABKD-AE EBR25UC8ABKD-AD EBR25UC8ABKD-8C 800 Organization 64M x 16 x 2 I/O Freq. (MHz) 1066 RAS access time (ns) Package 32 (32P) 32 35 40 232 edge connector pads RIMM with heat spreader Edge connector: Gold plated Mounted devices EBR25UC8ABKD Module Pad Names Pad A1 Signal name GND Pad B1 B2 B3 B4 B5 B6 B7 B8 Signal name GND CMD_THRU_L GND DQA7_THRU_L GND DQA5_THRU_L GND DQA3_THRU_L GND Pad A59 A60 A61 A62 A63 A64 A65 A66 A67 A68 A69 A70 A71 Signal name GND VTERM VTERM GND DQA3_THRU_R GND DQA5_THRU_R GND DQA7_THRU_R GND VDD GND SCK_THRU_R Pad B59 B60 B61 B62 B63 B64 B65 B66 B67 B68 B69 B70 B71 B72 B73 B74 B75 B76 B77 Signal name GND VTERM VTERM GND DQA4_THRU_R GND DQA6_THRU_R GND DQA8_THRU_R GND VDD GND CTMN_TERM_L GND CTM_TERM_L GND VCMOS VDD SWP VDD SDA VDD SA1 VDD SIN_TERM EO A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 SCK_THRU_L GND DQA8_THRU_L GND DQA6_THRU_L GND DQA4_THRU_L GND DQA2_THRU_L GND DQA0_THRU_L GND CFM_THRU_L GND CFMN_THRU_L GND ROW1_THRU_L GND COL4_THRU_L GND COL2_THRU_L GND COL0_THRU_L GND DQB1_THRU_L GND DQB3_THRU_L GND DQB5_THRU_L GND DQB7_THRU_L GND Preliminary Data Sheet E0309E11 (Ver. 1.1) L B9 B10 B11 GND B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 GND GND GND GND GND GND GND GND GND GND GND DQA1_THRU_L CTMN_THRU_L Pr CTM_THRU_L A72 GND A73 ROW2_THRU_L A74 GND A75 ROW0_THRU_L A76 VDD A77 COL3_THRU_L A78 VDD SCL A79 COL1_THRU_L A80 VDD SA0 A81 DQB0_THRU_L A82 VDD SA2 A83 DQB2_THRU_L A84 A85 A86 A87 A88 A89 A90 A91 GND DQB4_THRU_L GND DQB6_THRU_L GND DQB8_THRU_L GND CMD_THRU_R VREF od SVDD DQB8_TERM DQB6_TERM DQB4_TERM DQB2_TERM B78 B79 B80 B81 B82 B83 uc B84 GND B85 DQB7_TERM B86 GND B87 DQB5_TERM B88 GND B89 DQB3_TERM t B90 B91 GND DQB1_TERM 2 EBR25UC8ABKD Pad A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 Signal name SOUT_THRU GND DQB8_THRU_R GND DQB6_THRU_R GND DQB4_THRU_R GND DQB2_THRU_R GND DQB0_THRU_R GND Pad B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 B50 B51 B52 Signal name SIN_THRU GND DQB7_THRU_R GND DQB5_THRU_R GND DQB3_THRU_R GND DQB1_THRU_R GND COL0_THRU_R GND COL2_THRU_R GND COL4_THRU_R GND ROW1_THRU_R GND CFMN_THRU_R GND Pad A92 A93 A94 A95 A96 A97 A98 A99 A100 A101 A102 A103 A104 A105 A106 A107 A108 A109 A110 A111 A112 A113 A114 Signal name GND DQB0_TERM GND COL1_TERM GND COL3_TERM GND ROW0_TERM GND ROW2_TERM GND CTM_TERM_R GND CTMN_TERM_R GND DQA1_TERM GND DQA3_TERM GND DQA5_TERM GND DQA7_TERM GND Pad B92 B93 B94 B95 B96 B97 B98 B99 B100 B101 B102 B103 B104 B105 B106 B107 B108 B109 B110 B111 B112 B113 B114 B115 B116 Signal name GND COL0_TERM GND COL2_TERM GND COL4_TERM GND ROW1_TERM GND CFMN_TERM GND CFM_TERM GND DQA0_TERM GND DQA2_TERM GND DQA4_TERM GND DQA6_TERM GND DQA8_TERM GND SCK_TERM GND EO COL1_THRU_R GND A47 A48 COL3_THRU_R GND A49 A50 ROW0_THRU_R GND A51 A52 A53 A54 A55 A56 A57 A58 ROW2_THRU_R GND CTM_THRU_R GND CTMN_THRU_R GND DQA1_THRU_R Preliminary Data Sheet E0309E11 (Ver. 1.1) L B53 B54 B55 B56 B57 B58 GND GND CFM_THRU_R DQA0_THRU_R Pr A115 DQA2_THRU_R A116 GND CMD_TERM od uc t 3 EBR25UC8ABKD Module Connector Pad Description Signal CFM_THRU_L Module connector pads A14 I/O I Type RSL Description Clock From Master. Connects to left RDRAM device on "Thru" Channel. Interface clock used for receiving RSL signals from the controller. Positive polarity. Clock From Master. Connects to right RDRAM device on "Thru" Channel. Interface clock used for receiving RSL signals from the controller. Positive polarity. Clock From Master. Connects to left RDRAM device on "Thru" Channel. Interface clock used for receiving RSL signals from the controller. Negative polarity. Clock From Master. Connects to right RDRAM device on "Thru" Channel. Interface clock used for receiving RSL signals from the controller. Negative polarity. Serial Command Input used to read from and write to the control registers. Also used for power management. Connects to left RDRAM device on "Thru" Channel. Serial Command Input used to read from and write to the control registers. Also used for power management. Connects to right RDRAM device on "Thru" Channel. "Thru" Channel Column bus. 5-bit bus containing control and address information for column accesses. Connects to left RDRAM device on "Thru" Channel. "Thru" Channel Column bus. 5-bit bus containing control and address information for column accesses. Connects to right RDRAM device on "Thru" Channel. Clock To Master. Connects to left RDRAM device on "Thru" Channel. Interface clock used for transmitting RSL signals to the controller. Positive polarity. Clock To Master. Connects to right RDRAM device on "Thru" Channel. Interface clock used for transmitting RSL signals to the controller. Positive polarity. Clock To Master. Connects to left RDRAM device on "Thru" Channel. Interface clock used for transmitting RSL signals to the controller. Negative polarity. Clock To Master. Connects to right RDRAM device on "Thru" Channel. Interface clock used for transmitting RSL signals to the controller. Negative polarity. "Thru" Channel Data bus A. A 9-bit bus carrying a byte of read or write data between the controller and RDRAM devices on "Thru" Channel. Connects to left RDRAM device on "Thru" Channel. "Thru" Channel Data bus A. A 9-bit bus carrying a byte of read or write data between the controller and RDRAM devices on "Thru" Channel. Connects to right RDRAM device on "Thru" Channel. "Thru" Channel Data bus B. A 9-bit bus carrying a byte of read or write data between the controller and RDRAM devices on "Thru" Channel. Connects to left RDRAM device on "Thru" Channel. CFM_THRU_R B54 I RSL CFMN_THRU_L A16 I RSL CFMN_THRU_R B52 I RSL EO CMD_THRU_L B2 CMD_THRU_R A73 COL4_THRU_L.. COL0_THRU_L COL4_THRU_R.. COL0_THRU_R CTM_THRU_L B14 CTM_THRU_R A54 CTMN_THRU_L B12 CTMN_THRU_R A56 DQA8_THRU_L.. DQA0_THRU_L DQA8_THRU_R.. DQA0_THRU_R DQB8_THRU_L.. DQB0_THRU_L DQB8_THRU_R.. DQB0_THRU_R ROW2_THRU_L.. ROW0_THRU_L I VCMOS I VCMOS A20, B20, A22, B22, I A24 B48, A48, B46, A46, I B44 I RSL Preliminary Data Sheet E0309E11 (Ver. 1.1) L I I I A4, B4, A6, B6, A8, B8, A10, B10, A12 I/O B67, A67, B65, A65, B63, A63, B58, A58, I/O B56 B32, A32, B30, A30, B28, A28, B26, A26, I/O B24 A36, B36, A38, B38, A40, B40, A42, B42, I/O A44 B16, A18, B18 I RSL RSL RSL Pr RSL RSL RSL RSL RSL RSL RSL od 4 "Thru" Channel Data bus B. A 9-bit bus carrying a byte of read or write data between the controller and RDRAM devices on "Thru" Channel. Connects to right RDRAM device on "Thru" Channel. Row bus. 3-bit bus containing control and address information for row accesses. Connects to left RDRAM device on "Thru" Channel. uc t EBR25UC8ABKD Signal ROW2_THRU_R.. ROW0_THRU_R SCK_THRU_L Module connector pads A52, B50, A50 I/O I Type RSL Description Row bus. 3-bit bus containing control and address information for row accesses. Connects to right RDRAM device on "Thru" Channel. Serial Clock input. Clock source used to read from and write to "Thru" Channel RDRAM control registers. Connects to left RDRAM device on "Thru" Channel. Serial Clock input. Clock source used to read from and write to "Thru" Channel RDRAM control registers. Connects to right RDRAM device on "Thru" Channel. "Thru" Channel Serial I/O for reading from and writing to the control registers. Attaches to SIO0 of right RDRAM device on "Thru" Channel. "Thru" Channel Serial I/O for reading from and writing to the control registers. Attaches to SIO1 of left RDRAM device on "Thru" Channel. Clock from master. Connects to right RDRAM device on "Term" Channel. Interface clock used for receiving RSL signals from the controller. Positive polarity. Clock from master. Connects to right RDRAM device on "Term" Channel. Interface clock used for receiving RSL signals from the controller. Negative polarity. Serial Command Input used to read from and write to the control registers. Also used for power management. Connects to right RDRAM device on "Term" Channel. "Term" Channel Column bus. 5-bit bus containing control and address information for column accesses. Connects to right RDRAM device on "Term" Channel. Clock To Master. Connects to left RDRAM device on "Term" Channel. Interface clock used for transmitting RSL signals to the controller. Positive polarity. Clock To Master. Connects to right RDRAM device on "Term" Channel. Interface clock used for transmitting RSL signals to the controller. Positive polarity. Clock To Master. Connects to left RDRAM device on "Term" Channel. Interface clock used for transmitting RSL signals to the controller. Negative polarity. Clock To Master. Connects to right RDRAM device on "Term" Channel. Interface clock used for transmitting RSL signals to the controller. Negative polarity. "Term" Channel Data bus A. A 9-bit bus carrying a byte of read or write data between the controller and RDRAM devices on "Term" Channel. Connects to right RDRAM device on "Term" Channel. "Term" Channel Data bus B. A 9-bit bus carrying a byte of read or write data between the controller and RDRAM devices on "Term" Channel. Connects to right RDRAM device on "Term" Channel. "Term" Channel Row bus. 3-bit bus containing control and address information for row accesses. Connects to right RDRAM device on "Term" Channel. Serial Clock input. Clock source used to read from and write to "Term" Channel RDRAM control registers. Connects to right RDRAM device on "Term" Channel. "Term" Channel Serial I/O for reading from and writing to the control registers. Attaches to SIO0 of left RDRAM device on "Term" Channel. A2 I VCMOS SCK_THRU_R A71 I VCMOS SIN_THRU B34 I/O VCMOS EO SOUT_THRU A34 CFM_TERM B103 CFMN_TERM B101 CMD_TERM A115 COL4_TERM.. COL0_TERM CTM_TERM_L B73 CTM_TERM_R A103 CTMN_TERM_L B71 CTMN_TERM_R A105 DQA8_TERM.. DQA0_TERM B113, A113, B111, A111, B109, A109, B107, A107, B105 DQB8_TERM.. DQB0_TERM ROW2_TERM.. ROW0_TERM SCK_TERM A101, B99, A99 B115 SIN_TERM VTERM B83 A60, B60, A61, B61 Preliminary Data Sheet E0309E11 (Ver. 1.1) I/O VCMOS I RSL I RSL I VCMOS L B97, A97, B95, A95, I B93 I I I I I/O A85, B85, A87, B87, A89, B89, A91, B91, I/O A93 I I I/O RSL RSL Pr RSL RSL RSL RSL RSL RSL VCMOS VCMOS od 5 "Term" Channel Termination voltage. uc t EBR25UC8ABKD Signal Module connector pads A1, A3, A5, A7, A9, A11, A13, A15, A17, A19, A21, A23, A25, A27, A29, A31, A33, A35, A37, A39, A41, A43, A45, A47, A49, A51, A53, A55, A57, A59, A62, A64, A66, A68, A70, A72, A74, A84, A86, A88, A90, A92, A94, A96, A98, A100, A102, A104, A106, A108, A110, A112, A114, A116, B1, B3, B5, B7, B9, B11, B13, B15, B17, B19, B21, B23, B25, B27, B29, B31, B33, B35, B37, B39, B41, B43, B45, B47, B49, B51, B53, B55, B57, B59, B62, B64, B66, B68, B70, B72, B74, B84, B86, B88, B90, B92, B94, B96, B98, B100, B102, B104, B106, B108, B110, B112, B114, B116 I I I I I/O SVDD SVDD SVDD SVDD SVDD I/O Type Description GND Ground reference for RDRAM core and interface. EO SA0 SA1 SA2 A81 B81 A83 SCL A79 SDA B79 SVDD SWP VCMOS VDD VREF A77 B77 B75 A75 Serial Presence Detect Address 0 Serial Presence Detect Address 1. Serial Presence Detect Address 2. Serial Presence Detect Clock. Serial Presence Detect Data (Open Collector I/O). SPD Voltage. Used for signals SCL, SDA, SWE, SA0, SA1 and SA2. Serial Presence Detect Write Protect (active high). When low, the SPD can be written as well as read. CMOS I/O Voltage. Used for signals CMD, SCK, SIN, SOUT. Supply voltage for the RDRAM core and interface logic. Logic threshold reference voltage for both "Thru" Channel and "Term" Channel RSL signals. Preliminary Data Sheet E0309E11 (Ver. 1.1) L A69, B69, A76, B76, A78, B78, A80, B80, A82, B82 I SVDD Pr 6 od uc t EBR25UC8ABKD SOUT_THRU SCK_THRU_L CMD_THRU_L VREF EO SIO0 SIO1 SCK CMD VREF SIO0 SIO1 SCK CMD VREF SIN_THRU SCK_THRU_R CMD_THRU_R SIN_TERM SCK_TERM CMD_TERM Preliminary Data Sheet E0309E11 (Ver. 1.1) SIO0 SIO1 SCK CMD VREF SIO0 SIO1 SCK CMD VREF DQA8_THRU_L DQA7_THRU_L DQA6_THRU_L DQA5_THRU_L DQA4_THRU_L DQA3_THRU_L DQA2_THRU_L DQA1_THRU_L DQA0_THRU_L CFM_THRU_L CFMN_THRU_L CTM_THRU_L CTMN_THRU_L ROW2_THRU_L ROW1_THRU_L ROW0_THRU_L COL4_THRU_L COL3_THRU_L COL2_THRU_L COL1_THRU_L COL0_THRU_L DQB0_THRU_L DQB1_THRU_L DQB2_THRU_L DQB3_THRU_L DQB4_THRU_L DQB5_THRU_L DQB6_THRU_L DQB7_THRU_L DQB8_THRU_L DQA8 DQA7 DQA6 DQA5 DQA4 DQA3 DQA2 DQA1 DQA0 CFM CFMN CTM CTMN ROW2 ROW1 ROW0 COL4 COL3 COL2 COL1 COL0 DQB0 DQB1 DQB2 DQB3 DQB4 DQB5 DQB6 DQB7 DQB8 DQA8_THRU_R DQA7_THRU_R DQA6_THRU_R DQA5_THRU_R DQA4_THRU_R DQA3_THRU_R DQA2_THRU_R DQA1_THRU_R DQA0_THRU_R CFM_THRU_R CFMN_THRU_R CTM_THRU_R CTMN_THRU_R ROW2_THRU_R ROW1_THRU_R ROW0_THRU_R COL4_THRU_R COL3_THRU_R COL2_THRU_R COL1_THRU_R COL0_THRU_R DQB0_THRU_R DQB1_THRU_R DQB2_THRU_R DQB3_THRU_R DQB4_THRU_R DQB5_THRU_R DQB6_THRU_R DQB7_THRU_R DQB8_THRU_R DQA8 DQA7 DQA6 DQA5 DQA4 DQA3 DQA2 DQA1 DQA0 CFM CFMN CTM CTMN ROW2 ROW1 ROW0 COL4 COL3 COL2 COL1 COL0 DQB0 DQB1 DQB2 DQB3 DQB4 DQB5 DQB6 DQB7 DQB8 Left RDRAM Device of "Term" Channel Block Diagram L Pr DQA8 DQA7 DQA6 DQA5 DQA4 DQA3 DQA2 DQA1 DQA0 CFM CFMN CTM CTMN ROW2 ROW1 ROW0 COL4 COL3 COL2 COL1 COL0 DQB0 DQB1 DQB2 DQB3 DQB4 DQB5 DQB6 DQB7 DQB8 Left RDRAM Device of "Thru" Channel Right RDRAM Device of "Thru" Channel Right RDRAM Device of "Term" Channel od VTERM DQA8 DQA7 DQA6 DQA5 DQA4 DQA3 DQA2 DQA1 DQA0 CFM CFMN CTM CTMN ROW2 ROW1 ROW0 COL4 COL3 COL2 COL1 COL0 DQB0 DQB1 DQB2 DQB3 DQB4 DQB5 DQB6 DQB7 DQB8 DQA8_TERM DQA7_TERM DQA6_TERM DQA5_TERM DQA4_TERM DQA3_TERM DQA2_TERM DQA1_TERM DQA0_TERM CFM_TERM CFMN_TERM CTM_TERM_R CTMN_TERM_R ROW2_TERM ROW1_TERM ROW0_TERM COL4_TERM COL3_TERM COL2_TERM COL1_TERM COL0_TERM DQB0_TERM DQB1_TERM DQB2_TERM DQB3_TERM DQB4_TERM DQB5_TERM DQB6_TERM DQB7_TERM DQB8_TERM uc VCC SCL SDA WP U0 A1 A2 A0 SVDD SWP SCL SA0 SA1 SA2 Serial PD t SDA CTMN_TERM_L CTM_TERM_L 7 EBR25UC8ABKD Electrical Specifications Absolute Maximum Ratings Symbol VI,ABS VDD,ABS TSTORE Parameter Voltage applied to any RSL or CMOS signal pad with respect to GND Voltage on VDD with respect to GND Storage temperature min. -0.3 -0.5 -50 max. VDD + 0.3 VDD + 1.0 +100 Unit V V C Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. EO Symbol VDD VCMOS VREF SVDD VTERM DC Recommended Electrical Conditions Parameter and conditions Supply voltage *1 min. 2.50 - 0.13 2.50 - 0.13 1.8 - 0.1 1.4 - 0.2 2.2 1.89 - 0.09 max. 2.50 + 0.13 2.50 + 0.25 1.8 + 0.2 1.4 + 0.2 3.6 1.89 + 0.09 Unit V V CMOS I/O power supply at pad 2.5V controllers 1.8V controllers Note: 1. See Direct RDRAM datasheet for more details. Preliminary Data Sheet E0309E11 (Ver. 1.1) L Reference voltage *1 V V V Serial Presence Detector- positive power supply Termination Voltage Pr od uc t 8 EBR25UC8ABKD AC Electrical Specifications Symbol Z Parameter and Conditions *1 Grade min. 25.2 23.8 TBD TBD TBD typ. 28.0 28.0 max. 30.8 32.2 TBD TBD TBD TBD Unit ns ps ps ps Module Impedance of RSL signals Module Impedance of SCK and CMD signals TPD TPD TPD-CMOS TPD- SCK,CMD Average clock delay from finger to finger of all RSL clock *2 nets (CTM, CTMN,CFM, and CFMN) Propagation delay variation of RSL signals with respect *1, 3 to TPD Propagation delay variation of SCK signal with respect to *1 an average clock delay Propagation delay variation of CMD signal with respect to SCK signal Attenuation Limit -AEP -AE -AD -8C -AEP -AE -AD -8C -AEP -AE -AD -8C -AEP -AE -AD -8C EO V/VIN VXF/VIN VXB/VIN RDC Symbol TPD TBD % Forward crosstalk coefficient (300ps input rise time 20% - 80%) TBD % Backward crosstalk coefficient (300ps input rise time 20% - 80%) Notes 1. Specifications apply per channel. 2. TPD or Average clock delay is defined as the average delay from finger to finger of all RSL clock nets (CTM, CTMN, CFM, and CFMN). 3. If the RIMM module meets the following specification, then it is compliant to the specification. If the RIMM module does not meet these specifications, then the specification can be adjusted by the "Adjusted TPD Specification" table. Adjusted TPD Specification Parameter and conditions Propagation delay variation of RSL signals with respect to TPD L DC Resistance Limit TBD % TBD Pr 9 od Adjusted min./max. +/- [17+(18*N*Z0)] *1 Absolute max. TBD Unit ps min. TBD Note N = Number of RDRAM devices installed on the RIMM module. Z0 = delta Z0% = (max. Z0 - min. Z0) / (min. Z0) (max. Z0 and min. Z0 are obtained from the loaded (high impedance) impedance coupons of all RSL layers on the module.) uc t Preliminary Data Sheet E0309E11 (Ver. 1.1) EBR25UC8ABKD RIMM Module Current Profile IDD RIMM module power conditions Note1 Grade *2 max. Unit IDD1 One RDRAM device per channel in Read , balance in NAP mode IDD2 One RDRAM device per channel in Read , balance in Standby mode *2 IDD3 One RDRAM device per channel in Read , balance in Active mode *2 IDD4 One RDRAM device per channel in Write, balance in NAP mode IDD5 One RDRAM device per channel in Write, balance in Standby mode IDD6 One RDRAM device per channel in Write, balance in Active mode -AEP -AE -AD -8C -AEP -AE -AD -8C -AEP -AE -AD -8C -AEP -AE -AD -8C -AEP -AE -AD -8C -AEP -AE -AD -8C TBD mA TBD mA TBD mA EO TBD mA TBD mA TBD mA Notes 1. Actual power will depend on individual RDRAM component specifications, memory controller and usage patterns. Power does not include Refresh Current. 2. I/O current is a function of the % of 1's, to add I/O power for 50 % 1's for a x18 need to add 276mA for the following : VDD = 2.5V, VTERM = 1.8V, VREF = 1.4V and VDIL = VREF - 0.5V. Preliminary Data Sheet E0309E11 (Ver. 1.1) L Pr od uc t 10 EBR25UC8ABKD Physical Outline Unit: mm 4.00 0.10 R2.00 Pad A1 5.68 A 59.00 4.00 7.00 78.175 133.35 5.00 47.00 17.78 34.925 1.270.10 Pad A116 3.00 0.10 2.99 0.30 0.10 EO 4.46 Max detail of A part Preliminary Data Sheet E0309E11 (Ver. 1.1) L 0.80 R1.50 Note: The dimensions without tolerance specification use the default tolerance of 0.13. Pr 3.000.10 1.00 od 11 ECA-TS2-0083-01 uc t EBR25UC8ABKD CAUTION FOR HANDLING MEMORY MODULES When handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory ICs, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these components to prevent damaging them. In particular, do not push module cover or drop the modules in order to protect from mechanical defects, which would be electrical defects. When re-packing memory modules, be sure the modules are not touching each other. Modules in contact with other modules may cause excessive mechanical stress, which may damage the modules. MDE0202 NOTES FOR CMOS DEVICES EO 1 2 3 PRECAUTION AGAINST ESD FOR MOS DEVICES Exposing the MOS devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. MOS devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. MOS devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor MOS devices on it. HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES No connection for CMOS devices input pins can be a cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. The unused pins must be handled in accordance with the related specifications. STATUS BEFORE INITIALIZATION OF MOS DEVICES Power-on does not necessarily define initial status of MOS devices. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the MOS devices with reset function have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. MOS devices are not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for MOS devices having reset function. Preliminary Data Sheet E0309E11 (Ver. 1.1) L Pr 12 od uc CME0107 t EBR25UC8ABKD Rambus, RDRAM and the Rambus logo are registered trademarks of Rambus Inc. RIMM, SO-RIMM, RaSer and QRSL are trademarks of Rambus Inc. The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Elpida Memory, Inc. Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or third parties by or arising from the use of the products or information listed in this document. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida Memory, Inc. or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [Product applications] Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability. However, users are instructed to contact Elpida Memory's sales office before using the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. [Product usage] Design your application so that the product is used within the ranges and conditions guaranteed by Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the Elpida Memory, Inc. product. [Usage environment] This product is not designed to be resistant to electromagnetic waves or radiation. This product must be used in a non-condensing environment. If you export the products or technology described in this document that are controlled by the Foreign Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by U.S. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. If these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. EO Preliminary Data Sheet E0309E11 (Ver. 1.1) L Pr 13 od M01E0107 uc t |
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